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24th IEEE VLSI Test Symposium
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
Praveen Parvathala, Intel Corporation
Device scaling has resulted in higher and higher product frequencies. With issues like printability concerns, increased noise and decreased noise tolerance on the rise with every generation, it is becoming clear that we need to complement structural test content with functional content in order to test for delay defects and marginal circuits. This becomes further important as the focus shifts to low-power designs. The motivation for functional tests comes from concerns that structural test application does not replicate the precise operating conditions needed on the DUT in order to sift the good parts from the defective ones. Since during functional test, the DUT operating conditions (voltage, temperature, power droop, noise environment) are similar to the device specifications, the confidence in the detecting such small deviations (delay/marginality) is higher.
Citation:
Praveen Parvathala, "Session Abstract," vts, pp.158-159, 24th IEEE VLSI Test Symposium, 2006
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