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24th IEEE VLSI Test Symposium
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
ASCII Text
x 
 
Ajay Khoche, Mike Rodgers, Pete O?Neil, "Session Abstract," VLSI Test Symposium, IEEE, pp. 426, 24th IEEE VLSI Test Symposium, 2006.
 
 
BibTex
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@article{ 10.1109/VTS.2006.62,
author = {Ajay Khoche and Mike Rodgers and Pete O?Neil},
title = {Session Abstract},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2006},
isbn = {0-7695-2514-8},
pages = {426},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2006.62},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Session Abstract
SN - 0-7695-2514-8
SP
EP
A1 - Ajay Khoche,
A1 - Mike Rodgers,
A1 - Pete O?Neil,
PY - 2006
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Ajay Khoche, Semiconductor Test Solutions, Agilent Technologies
Mike Rodgers, Intel Corporation
Pete O?Neil, Avago Technologies
The role of ATE is changing from the traditional just go/no go classification to supporting yield learning and adaptive test methodologies as well. This new role demands additional functionalities (e.g. real-time test program control) from the tester as well as puts new requirements on the existing functionalities (e.g. throughput of error capture). This panel will discuss whether the existing ATE architectures are ready for these challenges and what changes need to be made if any to meet the requirements of new role.
Citation:
Ajay Khoche, Mike Rodgers, Pete O?Neil, "Session Abstract," vts, pp.426, 24th IEEE VLSI Test Symposium, 2006
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