24th IEEE VLSI Test Symposium A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis Berkeley, California April 30-May 04 ISBN: 0-7695-2514-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2006.6
The paper addresses the issue of transistor-level bridging fault diagnosis. While most of the previous bridging fault diagnosis work focuses on the gate-level bridging faults, this method provides a solution to intragate bridging faults diagnosis for the first time. Instead of using any transistor level simulation tools, we develop a transformation technique that allows transistor-level bridging faults to be diagnosed by the commonly used gate-level bridging faults diagnosis tools. Real diagnosis results from Philips designs are presented.
Citation:
Xinyue Fan, Will Moore, Camelia Hora, Mario Konijnenburg, Guido Gronthoud, "A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis," vts, pp.266-271, 24th IEEE VLSI Test Symposium, 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||