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24th IEEE VLSI Test Symposium
A Built-In Self-Repair Scheme for NOR-Type Flash Memory
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
Yu-Ying Hsiao, National Tsing Hua University, Taiwan
Chao-Hsun Chen, National Tsing Hua University, Taiwan
Cheng-Wen Wu, National Tsing Hua University, Taiwan
The strong demand of non-volatile memory for SOC and SIP applications has made flash memory increasingly important. However, deep submicron defects and process uncertainties are causing yield loss of memory products. To solve the yield issue, built-in self-repair (BISR) is widely believed to be cost effective. It is, however, non-trivial to implement BISR on flash memories. In this paper we propose a BISR scheme for NOR-type flash memory. The BISR scheme performs built-in selftest (BIST), built-in redundancy analysis (BIRA), as well as on-chip repair. A typical redundancy architecture for NOR-type flash memory is assumed, based on which we present a redundancy analysis (RA) algorithm. Experimental result shows that the proposed BISR scheme can effectively repair most defective memories.
Citation:
Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu, "A Built-In Self-Repair Scheme for NOR-Type Flash Memory," vts, pp.114-119, 24th IEEE VLSI Test Symposium, 2006
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