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24th IEEE VLSI Test Symposium
Modular Compactor of Test Responses
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
ASCII Text
x 
 
Wojciech Rajski, Janusz Rajski, "Modular Compactor of Test Responses," VLSI Test Symposium, IEEE, pp. 242-251, 24th IEEE VLSI Test Symposium, 2006.
 
 
BibTex
x
 
@article{ 10.1109/VTS.2006.48,
author = {Wojciech Rajski and Janusz Rajski},
title = {Modular Compactor of Test Responses},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2006},
isbn = {0-7695-2514-8},
pages = {242-251},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2006.48},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Modular Compactor of Test Responses
SN - 0-7695-2514-8
SP242
EP251
A1 - Wojciech Rajski,
A1 - Janusz Rajski,
PY - 2006
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Wojciech Rajski, Oregon State University
Janusz Rajski, *Mentor Graphics Corporation
This paper describes a new time compactor built of multiple-input circular registers of relatively prime length. It has excellent ability to detect errors corresponding to real defects such as errors of small multiplicity and burst errors. It operates in modular arithmetic and uses the Chinese remaindering to diagnose scan errors. Given that circular registers do not multiply errors or X values, the compactor is X toleran
Citation:
Wojciech Rajski, Janusz Rajski, "Modular Compactor of Test Responses," vts, pp.242-251, 24th IEEE VLSI Test Symposium, 2006
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