24th IEEE VLSI Test Symposium Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing Berkeley, California April 30-May 04 ISBN: 0-7695-2514-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2006.45
Classical test approaches typically provide abysmally low path delay fault coverage for high-speed latch-based circuits where time borrowing may occur. Furthermore, none of the classical design-for-testability (DFT) approaches can be used to improve coverage. In [1] we proposed the first structural testing approach that can provide high robust path delay fault coverage for such circuits. However, that approach suffered from high DFT overheads since it required a fully-reconfigurable scan circuitry. In this paper we propose an approach that can provide even higher path delay fault coverage for such circuits using dramatically fewer scan configurations. The proposed test generation approach can also provide high path delay fault coverage under any given set of scan chain configurations. We demonstrate the benefits of the proposed approach via extensive experiments.
Citation:
Kun Young Chung, Sandeep K. Gupta, "Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing," vts, pp.8-15, 24th IEEE VLSI Test Symposium, 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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