Investigating the Efficiency of Integrator-Based Capacitor Array Testing Techniques

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24th IEEE VLSI Test Symposium

Berkeley, California

April 30-May 04

ISBN: 0-7695-2514-8

	ASCII Text	x
	Sai Raghuram Durbha, Amit Laknaur, Haibo Wang, "Investigating the Efficiency of Integrator-Based Capacitor Array Testing Techniques," VLSI Test Symposium, IEEE, pp. 320-325, 24th IEEE VLSI Test Symposium, 2006.

	BibTex	x
	@article{ 10.1109/VTS.2006.42, author = {Sai Raghuram Durbha and Amit Laknaur and Haibo Wang}, title = {Investigating the Efficiency of Integrator-Based Capacitor Array Testing Techniques}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2006}, isbn = {0-7695-2514-8}, pages = {320-325}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2006.42}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Investigating the Efficiency of Integrator-Based Capacitor Array Testing Techniques SN - 0-7695-2514-8 SP320 EP325 A1 - Sai Raghuram Durbha, A1 - Amit Laknaur, A1 - Haibo Wang, PY - 2006 KW - null VL - 0 JA - VLSI Test Symposium, IEEE ER -

Sai Raghuram Durbha, Southern Illinois University

Amit Laknaur, Southern Illinois University

Haibo Wang, Southern Illinois University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2006.42

This paper presents techniques to model the impact of parametric faults on the performance of programmable capacitor arrays (PCAs). Closed-form equations are derived for estimating ranges of parametric faults that can be detected by integrator-based PCA testing circuits. Methods to improve PCA testing efficiency are discussed and experimental results are reported.

Citation:

Sai Raghuram Durbha, Amit Laknaur, Haibo Wang, "Investigating the Efficiency of Integrator-Based Capacitor Array Testing Techniques," vts, pp.320-325, 24th IEEE VLSI Test Symposium, 2006

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