Improving Gate-Level ATPG by Traversing Concurrent EFSMs

V
VTS
2006
24th IEEE VLSI Test Symposium
Abstract - Improving Gate-Level ATPG by Traversing Concurrent EFSMs

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Giuseppe Di Guglielmo Articles by Franco Fummi Articles by Cristina Marconcini Articles by Graziano Pravadelli

24th IEEE VLSI Test Symposium

Berkeley, California

April 30-May 04

ISBN: 0-7695-2514-8

	ASCII Text	x
	Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli, "Improving Gate-Level ATPG by Traversing Concurrent EFSMs," VLSI Test Symposium, IEEE, pp. 172-179, 24th IEEE VLSI Test Symposium, 2006.

	BibTex	x
	@article{ 10.1109/VTS.2006.39, author = {Giuseppe Di Guglielmo and Franco Fummi and Cristina Marconcini and Graziano Pravadelli}, title = {Improving Gate-Level ATPG by Traversing Concurrent EFSMs}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2006}, isbn = {0-7695-2514-8}, pages = {172-179}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2006.39}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Improving Gate-Level ATPG by Traversing Concurrent EFSMs SN - 0-7695-2514-8 SP172 EP179 A1 - Giuseppe Di Guglielmo, A1 - Franco Fummi, A1 - Cristina Marconcini, A1 - Graziano Pravadelli, PY - 2006 KW - null VL - 0 JA - VLSI Test Symposium, IEEE ER -

Giuseppe Di Guglielmo, Universita di Verona, Italy

Franco Fummi, Universita di Verona, Italy

Cristina Marconcini, Universita di Verona, Italy

Graziano Pravadelli, Universita di Verona, Italy

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2006.39

The paper describes an high-level pseudo-deterministic ATPG that explores the DUT state space by exploiting an easy-totraverse extended FSM model. Testing of hard-to-detect faults is thus improved. Generated test sequences are very effective in detecting both high-level faults and gate-level stuck-at faults. Thus, the reuse of test sequences generated by the proposed ATPG allows to improve the stuck-at fault coverage and to reduce the execution time of commercial gate-level ATPGs.

Citation:

Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli, "Improving Gate-Level ATPG by Traversing Concurrent EFSMs," vts, pp.172-179, 24th IEEE VLSI Test Symposium, 2006

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.