This paper proposes a technique for testing small delay defects that incorporates the use of standard transition delay ATPG along with timing information gathered from standard static timing analysis (STA), in order to obtain a high defect coverage of the small delay defects that lie along the critical paths of a given design. This technique takes advantage of the fact that transition delay APTG can easily create patterns for node-based delay defects, and it then uses the timing information gathered from STA to ensure that the patterns that test given paths are grouped with like patterns and are tested at near maximum frequency. We present the experimental results, which demonstrate the effectiveness of this technique to detect small delay defects using transition