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24th IEEE VLSI Test Symposium
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
Vishnu C. Vimjam, Virginia Tech
Michael S. Hsiao, Virginia Tech
Fault collapsing of a fault-set helps in obtaining smaller test-sets as well as in reducing fault-simulation times. In this paper, we propose two new theorems by making use of the generalized dominance relations exhibited by a pair of faults. In order to learn several unique requirements for the faults in a low-cost manner, we employ a fault-independent analysis and propose heuristics to reduce the number of fault-pair comparisons required. Experimental results on ISCAS85, 89 & 93 benchmarks show that significantly more faults can be collapsed as compared to the existing methods, with smaller run-times in many cases. For most circuits, collapsing to less than 30% of the total number of faults is achieved.
Citation:
Vishnu C. Vimjam, Michael S. Hsiao, "Efficient Fault Collapsing via Generalized Dominance Relations," vts, pp.258-265, 24th IEEE VLSI Test Symposium, 2006
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