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24th IEEE VLSI Test Symposium
Dominance Based Analysis for Large Volume Production Fail Diagnosis
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
B. Seshadri, Purdue University
I. Pomeranz, Purdue University
S. Venkataraman, Intel Corporation
M.E. Amyeen, Intel Corporation
S.M. Reddy, University of Iowa
A procedure for using fault dominance in a large volume diagnosis environment is described. Fault dominance is shown to be useful for reducing the fault simulation time during diagnosis when used together with the concept of pattern dependence and maximally dominating faults. Results for both ISCAS benchmarks and industrial circuits are reported. The results show 9% to 44% average reduction in the fault simulation time for these circuits.
Citation:
B. Seshadri, I. Pomeranz, S. Venkataraman, M.E. Amyeen, S.M. Reddy, "Dominance Based Analysis for Large Volume Production Fail Diagnosis," vts, pp.392-399, 24th IEEE VLSI Test Symposium, 2006
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