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24th IEEE VLSI Test Symposium
Design Optimization for Robustness to Single Event Upsets
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
ASCII Text
x 
 
Quming Zhou, Mihir R. Choudhury, Kartik Mohanram, "Design Optimization for Robustness to Single Event Upsets," VLSI Test Symposium, IEEE, pp. 202-207, 24th IEEE VLSI Test Symposium, 2006.
 
 
BibTex
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@article{ 10.1109/VTS.2006.28,
author = {Quming Zhou and Mihir R. Choudhury and Kartik Mohanram},
title = {Design Optimization for Robustness to Single Event Upsets},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2006},
isbn = {0-7695-2514-8},
pages = {202-207},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2006.28},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Design Optimization for Robustness to Single Event Upsets
SN - 0-7695-2514-8
SP202
EP207
A1 - Quming Zhou,
A1 - Mihir R. Choudhury,
A1 - Kartik Mohanram,
PY - 2006
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Quming Zhou, Rice University
Mihir R. Choudhury, Rice University
Kartik Mohanram, Rice University
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model is integrated with area and performance constraints into an optimization framework based on geometric programming for design space exploration. Simulation results demonstrate the design tradeoffs that can be achieved with this approach.
Citation:
Quming Zhou, Mihir R. Choudhury, Kartik Mohanram, "Design Optimization for Robustness to Single Event Upsets," vts, pp.202-207, 24th IEEE VLSI Test Symposium, 2006
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