24th IEEE VLSI Test Symposium An Overview of Failure Mechanisms in Embedded Flash Memories Berkeley, California April 30-May 04 ISBN: 0-7695-2514-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2006.19
Non-volatile Flash memories are becoming more and more popular for System-on-Chip design (SoC). Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. Studies of realistic failure mechanisms and their associated fault models are the first mandatory step before providing efficient and practical new test methods. In this paper, we present an analysis made on actual failures occurring in 2T FLOTOX cells of 0.15?m NOR-based embedded flash structure.
Citation:
O. Ginez, J.-M. Daga, M. Combe, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, "An Overview of Failure Mechanisms in Embedded Flash Memories," vts, pp.108-113, 24th IEEE VLSI Test Symposium, 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||