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24th IEEE VLSI Test Symposium
An Overview of Failure Mechanisms in Embedded Flash Memories
Berkeley, California
April 30-May 04
ISBN: 0-7695-2514-8
O. Ginez, ATMEL Rousset, France
J.-M. Daga, ATMEL Rousset, France
M. Combe, ATMEL Rousset, France
P. Girard, Universit? de Montpellier, France
C. Landrault, Universit? de Montpellier, France
S. Pravossoudovitch, Universit? de Montpellier, France
A. Virazel, Universit? de Montpellier, France
Non-volatile Flash memories are becoming more and more popular for System-on-Chip design (SoC). Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. Studies of realistic failure mechanisms and their associated fault models are the first mandatory step before providing efficient and practical new test methods. In this paper, we present an analysis made on actual failures occurring in 2T FLOTOX cells of 0.15?m NOR-based embedded flash structure.
Citation:
O. Ginez, J.-M. Daga, M. Combe, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, "An Overview of Failure Mechanisms in Embedded Flash Memories," vts, pp.108-113, 24th IEEE VLSI Test Symposium, 2006
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