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23rd IEEE VLSI Test Symposium (VTS'05)
Transition Tests for High Performance Microprocessors
Palm Springs, California
May 01-May 05
ISBN: 0-7695-2314-5
Yi-Shing Chang, Intel Corporation
Sreejit Chakravarty, Intel Corporation
Hiep Hoang, Intel Corporation
Nick Thorpe, Intel Corporation
Khen Wee, Intel Corporation
The scope and need for scan based transition tests in the context of high volume manufacturing testing of microprocessors is discussed. A classification of transition faults for latch based design is presented. Finally, we discuss a silicon experiment to understand the most fundamental issue of scan based transition testing viz. their robustness.
Citation:
Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee, "Transition Tests for High Performance Microprocessors," vts, pp.29-34, 23rd IEEE VLSI Test Symposium (VTS'05), 2005
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