Test and Characterization of a Variable-Capacity Multilevel DRAM

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23rd IEEE VLSI Test Symposium (VTS'05)

Palm Springs, California

May 01-May 05

ISBN: 0-7695-2314-5

	ASCII Text	x
	John C. Koob, Sue A. Ung, Ashwin S. Rao, Daniel A. Leder, Craig S. Joly, Kristopher C. Breen, Tyler Brandon, Michael Hume, Bruce F. Cockburn, Duncan G. Elliott, "Test and Characterization of a Variable-Capacity Multilevel DRAM," VLSI Test Symposium, IEEE, pp. 189-197, 23rd IEEE VLSI Test Symposium (VTS'05), 2005.

	BibTex	x
	@article{ 10.1109/VTS.2005.82, author = {John C. Koob and Sue A. Ung and Ashwin S. Rao and Daniel A. Leder and Craig S. Joly and Kristopher C. Breen and Tyler Brandon and Michael Hume and Bruce F. Cockburn and Duncan G. Elliott}, title = {Test and Characterization of a Variable-Capacity Multilevel DRAM}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2005}, issn = {1093-0167}, pages = {189-197}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2005.82}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Test and Characterization of a Variable-Capacity Multilevel DRAM SN - 1093-0167 SP189 EP197 A1 - John C. Koob, A1 - Sue A. Ung, A1 - Ashwin S. Rao, A1 - Daniel A. Leder, A1 - Craig S. Joly, A1 - Kristopher C. Breen, A1 - Tyler Brandon, A1 - Michael Hume, A1 - Bruce F. Cockburn, A1 - Duncan G. Elliott, PY - 2005 KW - null VL - 0 JA - VLSI Test Symposium, IEEE ER -

John C. Koob, University of Alberta

Sue A. Ung, University of Alberta

Ashwin S. Rao, University of Alberta

Daniel A. Leder, University of Alberta

Craig S. Joly, University of Alberta

Kristopher C. Breen, University of Alberta

Tyler Brandon, University of Alberta

Michael Hume, University of Alberta

Bruce F. Cockburn, University of Alberta

Duncan G. Elliott, University of Alberta

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2005.82

Multilevel DRAM (MLDRAM) increases the storage density of DRAMs by using more than two data signal levels in the storage cells. An operational 19200-cell MLDRAM in 1.8-V, 0.18-μm mixed-signal CMOS is described that allows 1, 1.5, 2, 2.25 and 2.5 bits-percell operation using 2, 3, 4, 5 and 6 data signal levels, respectively. The MLDRAM uses reference and data cell signals that are generated in the cell array using charge sharing. The single-step sensing method uses multiple reference signals in parallel. Test chip characterization features include four cell sizes, two sense amplifier sizes, and bitline shields for half of the cells. New tests were developed based on an MLDRAM fault model. These include basic functionality, retention time, multilevel march, inter-bitline coupling, and cell-plate voltage bump tests. Our results show that the data and reference signals are generated correctly and that MLDRAM is possible for up to six signal levels.

Citation:

John C. Koob, Sue A. Ung, Ashwin S. Rao, Daniel A. Leder, Craig S. Joly, Kristopher C. Breen, Tyler Brandon, Michael Hume, Bruce F. Cockburn, Duncan G. Elliott, "Test and Characterization of a Variable-Capacity Multilevel DRAM," vts, pp.189-197, 23rd IEEE VLSI Test Symposium (VTS'05), 2005

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