23rd IEEE VLSI Test Symposium (VTS'05) Soft Error Mitigation for SRAM-Based FPGAs Palm Springs, California May 01-May 05 ISBN: 0-7695-2314-5
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2005.75
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs, since SEUs in configuration bits of FPGAs result in permanent errors in the mapped design. Moreover, the number of sensitive configuration bits is two orders of magnitude more than user bits in typical FPGA-based circuits. In this paper, we present a high-reliable low-cost mitigation technique which can significantly improve the availability of designs mapped into FPGAs. Experimental results show that, using this technique, the availability of an FPGA mapped design can be increases to more than 99%.
Citation:
Ghazanfar-Hossein Asadi, Mehdi Baradaran Tahoori, "Soft Error Mitigation for SRAM-Based FPGAs," vts, pp.207-212, 23rd IEEE VLSI Test Symposium (VTS'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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