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23rd IEEE VLSI Test Symposium (VTS'05)
Segmented Addressable Scan Architecture
Palm Springs, California
May 01-May 05
ISBN: 0-7695-2314-5
ASCII Text
x 
 
Ahmad Al-Yamani, Erik Chmelar, Mikhail Grinchuck, "Segmented Addressable Scan Architecture," VLSI Test Symposium, IEEE, pp. 405-411, 23rd IEEE VLSI Test Symposium (VTS'05), 2005.
 
 
BibTex
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@article{ 10.1109/VTS.2005.74,
author = {Ahmad Al-Yamani and Erik Chmelar and Mikhail Grinchuck},
title = {Segmented Addressable Scan Architecture},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2005},
issn = {1093-0167},
pages = {405-411},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2005.74},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Segmented Addressable Scan Architecture
SN - 1093-0167
SP405
EP411
A1 - Ahmad Al-Yamani,
A1 - Erik Chmelar,
A1 - Mikhail Grinchuck,
PY - 2005
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Ahmad Al-Yamani, LSI Logic Corporation
Erik Chmelar, LSI Logic Corporation
Mikhail Grinchuck, LSI Logic Corporation
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consumption, and tester channel requirements. With minimal hardware overhead, the architecture provides at least an order of magnitude reduction to each of the above problems. The architecture relies on scan chain segmentation and multiple-hot decoders.
Citation:
Ahmad Al-Yamani, Erik Chmelar, Mikhail Grinchuck, "Segmented Addressable Scan Architecture," vts, pp.405-411, 23rd IEEE VLSI Test Symposium (VTS'05), 2005
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