The exponential increase in the number of transistors implemented in integrated circuits in each new generation of CMOS technology is causing an explosion not only in functional power consumption but in test power consumption as well. Although most research has focused mainly on reducing average power or the total energy consumed during test, instantaneous power consumption is also increasing and posing a serious threat for the ability of a chip to be tested in a manufacturing test floor - or worse in field testing using built-in-self-test (BIST) where battery-powered applications lack the supply voltage robustness of automated test equipment (ATE). In this paper, a flip-flop design is proposed that is the cornerstone of a novel scan clocking architecture inspired by the need to reduce instantaneous power during scan.