23rd IEEE VLSI Test Symposium (VTS'05) On Low-Capture-Power Test Generation for Scan Testing Palm Springs, California May 01-May 05 ISBN: 0-7695-2314-5
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2005.60
Research on low-power scan testing has been focused on the shift mode, with little or no consideration given to the capture mode power. However, high switching activity when capturing a test response can cause excessive IR drop, resulting in significant yield loss. This paper addresses this problem with a novel low-capture-power X-filling method by assigning 0?s and 1?s to unspecified (X) bits in a test cube to reduce the switching activity in capture mode. This method can be easily incorporated into any test generation flow, where test cubes are obtained during ATPG or by Xbit identification. Experimental results show the effectiveness of this method in reducing capture power dissipation without any impact on area, timing, and fault coverage.
Citation:
Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita, "On Low-Capture-Power Test Generation for Scan Testing," vts, pp.265-270, 23rd IEEE VLSI Test Symposium (VTS'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||