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23rd IEEE VLSI Test Symposium (VTS'05)
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS
Palm Springs, California
May 01-May 05
ISBN: 0-7695-2314-5
ASCII Text
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Qikai Chen, Hamid Mahmoodi, Swarup Bhunia, Kaushik Roy, "Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS," VLSI Test Symposium, IEEE, pp. 292-297, 23rd IEEE VLSI Test Symposium (VTS'05), 2005.
 
 
BibTex
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@article{ 10.1109/VTS.2005.58,
author = {Qikai Chen and Hamid Mahmoodi and Swarup Bhunia and Kaushik Roy},
title = {Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2005},
issn = {1093-0167},
pages = {292-297},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2005.58},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS
SN - 1093-0167
SP292
EP297
A1 - Qikai Chen,
A1 - Hamid Mahmoodi,
A1 - Swarup Bhunia,
A1 - Kaushik Roy,
PY - 2005
KW - DFT
KW - Failure mechanixm
KW - March Test
KW - Process Variation
KW - SRAM
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Qikai Chen, Purdue University
Hamid Mahmoodi, Purdue University
Swarup Bhunia, Purdue University
Kaushik Roy, Purdue University
In this paper, we have made a complete analysis of the emerging SRAM failure mechanisms due to process variations and mapped them to fault models. We have proposed two efficient test solutions for the process variation related failures in SRAM: (a) modification of March sequence, and (b) a novel low-overhead DFT circuit to complement the March test for an overall test time reduction of 29%, compared to the existing test technique with similar fault coverage.
Index Terms:
DFT, Failure mechanixm, March Test, Process Variation, SRAM
Citation:
Qikai Chen, Hamid Mahmoodi, Swarup Bhunia, Kaushik Roy, "Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS," vts, pp.292-297, 23rd IEEE VLSI Test Symposium (VTS'05), 2005
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