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23rd IEEE VLSI Test Symposium (VTS'05)
Modeling and Testing Comparison Faults for Ternary Content Addressable Memories
Palm Springs, California
May 01-May 05
ISBN: 0-7695-2314-5
ASCII Text
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Jin-Fu Li, Chou-Kun Lin, "Modeling and Testing Comparison Faults for Ternary Content Addressable Memories," VLSI Test Symposium, IEEE, pp. 60-65, 23rd IEEE VLSI Test Symposium (VTS'05), 2005.
 
 
BibTex
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@article{ 10.1109/VTS.2005.57,
author = {Jin-Fu Li and Chou-Kun Lin},
title = {Modeling and Testing Comparison Faults for Ternary Content Addressable Memories},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2005},
issn = {1093-0167},
pages = {60-65},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2005.57},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Modeling and Testing Comparison Faults for Ternary Content Addressable Memories
SN - 1093-0167
SP60
EP65
A1 - Jin-Fu Li,
A1 - Chou-Kun Lin,
PY - 2005
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Jin-Fu Li, National Central University
Chou-Kun Lin, National Central University
This paper presents the comparison faults of TCAMs based on physical defects, such as shorts between two circuit nodes and transistor stuck-open and stuck-on faults. Accordingly, several comparison fault models are proposed. A March-like test algorithm for comparison faults is also proposed. The test algorithm only requires 4N Write operations, 3N Erase operations, and (4N+2B) Compare operations to cover 100% comparison faults for an N x B-bit TCAM. Compared with the previous work, the proposed test algorithm has lower time complexity for TCAMs with wide words and the time complexity is independent of the number of stuck-on faults. Also, the algorithm can cover all defects that cause a failed Compare operation. Moreover, it can be realized by built-in self-test circuitry with lower area cost.
Citation:
Jin-Fu Li, Chou-Kun Lin, "Modeling and Testing Comparison Faults for Ternary Content Addressable Memories," vts, pp.60-65, 23rd IEEE VLSI Test Symposium (VTS'05), 2005
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