This paper addresses delay test for SOC devices on low-cost testers. The case study focuses on the at-speed testing for a state-of-the-art micro-controller device by using an on-chip high-speed clock generator. The experimental results show that the simple on-chip highspeed clock generator is not sufficient to reach both high fault coverage and acceptable pattern count. Meanwhile, at-speed test constraints, required to enable the delay test on low cost testers, have a significant impact on test generation results. DFT techniques to increase fault coverage and to reduce pattern count are discussed.