23rd IEEE VLSI Test Symposium (VTS'05) A BIST Scheme for FPGA Interconnect Delay Faults Palm Springs, California May 01-May 05 ISBN: 0-7695-2314-5
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2005.5
In this paper, we propose a new BIST-based approach for testing FPGA interconnect delay faults. The BIST architecture utilizes the regularity of an FPGA by implementing small test circuits repetitively over FPGA's CLB arrays. Each test circuit targets a specific path and determine conformance of the path delay according to a test clock. With the target path configured as a loop back in the test circuit, test accuracy of the path delay can be increased with reduced effects from skews of the test clocks. Thus, this BIST has a higher delay fault coverage, since it is not necessary to apply guard bands for skews in test mode.
Citation:
Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu, "A BIST Scheme for FPGA Interconnect Delay Faults," vts, pp.201-206, 23rd IEEE VLSI Test Symposium (VTS'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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