We present a methodology for diagnosing arbitrary defects in digital integrated circuits (ICs). Rather than using one or a set of fault models in a cause-effect or effect-cause approach, our methodology derives defect behavior from the test set, the circuit and its response, and the physical neighbors that surround a potential defect location. The defect locations themselves are identified using a model-independent stage. The methodology enables accurate identification of defect location and behavior through validation via simulation using passing and additional diagnostic test patterns. A byproduct of our methodology is the distinction that can be made among stuck-fault equivalencies which results in improved diagnostic resolution. Several types of shorts and opens are used to demonstrate the applicability of our approach to the diagnosis of arbitrary defects.