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23rd IEEE VLSI Test Symposium (VTS'05)
Closed-Form Simulation and Robustness Models for SEU-Tolerant Design
Palm Springs, California
May 01-May 05
ISBN: 0-7695-2314-5
ASCII Text
x 
 
Kartik Mohanram, "Closed-Form Simulation and Robustness Models for SEU-Tolerant Design," VLSI Test Symposium, IEEE, pp. 327-333, 23rd IEEE VLSI Test Symposium (VTS'05), 2005.
 
 
BibTex
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@article{ 10.1109/VTS.2005.35,
author = {Kartik Mohanram},
title = {Closed-Form Simulation and Robustness Models for SEU-Tolerant Design},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2005},
issn = {1093-0167},
pages = {327-333},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2005.35},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Closed-Form Simulation and Robustness Models for SEU-Tolerant Design
SN - 1093-0167
SP327
EP333
A1 - Kartik Mohanram,
PY - 2005
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Kartik Mohanram, Rice University
A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SPICE-based calibration of logic gates for a range of values of fanout, charge, and scale factor is presented. A full set of experimental results demonstrate that on average, the model is accurate to within 5% of the results obtained using SPICE with over 100X improvement in computational speed. Besides simulation and analysis of SEU-induced transients, the proposed model can be used to perform reliability-aware logic synthesis through the incorporation of robustness metrics to tune cell libraries.
Citation:
Kartik Mohanram, "Closed-Form Simulation and Robustness Models for SEU-Tolerant Design," vts, pp.327-333, 23rd IEEE VLSI Test Symposium (VTS'05), 2005
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