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23rd IEEE VLSI Test Symposium (VTS'05)
At-Speed Transition Fault Testing With Low Speed Scan Enable
Palm Springs, California
May 01-May 05
ISBN: 0-7695-2314-5
Nisar Ahmed, Texas Instruments India
C. P. Ravikumar, Texas Instruments India
Mohammad Tehranipoor, Texas Instruments India
Jim Plusquellic, Texas Instruments India
With today's design size in millions of gates and working frequency in gigahertz range, at-speed test is crucial. The launch-off-shift method has several advantages over the launch-off-capture but imposes strict requirements on transition fault testing due to at-speed scan enable signal. A novel scan-based at-speed test is proposed which generates multiple local fast scan enable signals. The scan enable control information is encapsulated in the test data and transferred during the scan operation. A new scan cell, referred to as last transition generator (LTG), is inserted in the scan chains to generate the fast local scan enable signal. The proposed technique is robust, practice-oriented and suitable for use in an industrial flow.
Citation:
Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic, "At-Speed Transition Fault Testing With Low Speed Scan Enable," vts, pp.42-47, 23rd IEEE VLSI Test Symposium (VTS'05), 2005
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