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23rd IEEE VLSI Test Symposium (VTS'05)
An Efficient Random Jitter Measurement Technique Using Fast Comparator Sampling
Palm Springs, California
May 01-May 05
ISBN: 0-7695-2314-5
Dongwoo Hong, University of California at Santa Barbara
Cameron Dryden, Metrologic Instruments
Gordon Saksena, Teradyne Corp.
This paper describes a random jitter measurement technique using simple algorithms and comparator sampling. The approach facilitates using Automated Test Equipment (ATE) to validate devices with multiple, high-speed serial interfaces. The approach combines partial measurements based on individual data edge regions, in contrast to more common approaches that effectively first accumulate data from multiple edge regions. Random jitter is measured accurately even in the presence of deterministic and low-frequency periodic jitter, up to a cutoff frequency.
Citation:
Dongwoo Hong, Cameron Dryden, Gordon Saksena, "An Efficient Random Jitter Measurement Technique Using Fast Comparator Sampling," vts, pp.123-130, 23rd IEEE VLSI Test Symposium (VTS'05), 2005
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