Speeding-Up IDDQ Measurements

V
VTS
2002
20th IEEE VLSI Test Symposium
Abstract - Speeding-Up IDDQ Measurements

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20th IEEE VLSI Test Symposium

Monterey, California

April 28-May 02

ISBN: 0-7695-1570-3

	ASCII Text	x
	C. Thibeault, "Speeding-Up IDDQ Measurements," VLSI Test Symposium, IEEE, pp. 0295, 20th IEEE VLSI Test Symposium, 2002.

	BibTex	x
	@article{ 10.1109/VTS.2002.1011157, author = {C. Thibeault}, title = {Speeding-Up IDDQ Measurements}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2002}, isbn = {0-7695-1570-3}, pages = {0295}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011157}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Speeding-Up IDDQ Measurements SN - 0-7695-1570-3 SP EP A1 - C. Thibeault, PY - 2002 VL - 0 JA - VLSI Test Symposium, IEEE ER -

C. Thibeault, ?cole de Technologie Sup?rieure

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011157

The purpose of this paper is to introduce a new IDDQ measurement technique based on active successive approximations,named ASA-IDDQ. This technique has unique features allowing to speed-up IDDQ measurement. Experimental results suggests that a significant speed-up factor can be obtained over the QuiC-Mon technique.

Citation:

C. Thibeault, "Speeding-Up IDDQ Measurements," vts, pp.0295, 20th IEEE VLSI Test Symposium, 2002

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