20th IEEE VLSI Test Symposium Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division Monterey, California April 28-May 02 ISBN: 0-7695-1570-3
This paper presents a new method fo measuring timing jitter of the bit clock signal in telecommunication devices operating at 10 Gbps. The method uses a divide-by-M circuit to reduce the frequency and the number of clock samples, and applies the Hilbert transform to measure the timing jitter. The theory fo this frequency division method is supported by the experimental data from a serializer-deserializer device.
Citation:
Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha, "Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division," vts, pp.0207, 20th IEEE VLSI Test Symposium, 2002 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||