On Using Efficient Test Sequences for BIST

V
VTS
2002
20th IEEE VLSI Test Symposium
Abstract - On Using Efficient Test Sequences for BIST

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by R. David Articles by P. Girard Articles by C. Landrault Articles by S. Pravossoudovitch Articles by A. Virazel

20th IEEE VLSI Test Symposium

Monterey, California

April 28-May 02

ISBN: 0-7695-1570-3

	ASCII Text	x
	R. David, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, "On Using Efficient Test Sequences for BIST," VLSI Test Symposium, IEEE, pp. 0145, 20th IEEE VLSI Test Symposium, 2002.

	BibTex	x
	@article{ 10.1109/VTS.2002.1011126, author = {R. David and P. Girard and C. Landrault and S. Pravossoudovitch and A. Virazel}, title = {On Using Efficient Test Sequences for BIST}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2002}, isbn = {0-7695-1570-3}, pages = {0145}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011126}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - On Using Efficient Test Sequences for BIST SN - 0-7695-1570-3 SP EP A1 - R. David, A1 - P. Girard, A1 - C. Landrault, A1 - S. Pravossoudovitch, A1 - A. Virazel, PY - 2002 VL - 0 JA - VLSI Test Symposium, IEEE ER -

R. David, Laboratoire d ?Automatique de Grenoble

P. Girard, Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier

C. Landrault, Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier

S. Pravossoudovitch, Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier

A. Virazel, Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011126

High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution.

Citation:

R. David, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, "On Using Efficient Test Sequences for BIST," vts, pp.0145, 20th IEEE VLSI Test Symposium, 2002

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.