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20th IEEE VLSI Test Symposium
Scan-Path with Directly Duplicated and Inverted Duplicated Registers
Monterey, California
April 28-May 02
ISBN: 0-7695-1570-3
ASCII Text
x 
 
M. Goessel, E. Sogomonyan, A. Singh, "Scan-Path with Directly Duplicated and Inverted Duplicated Registers," VLSI Test Symposium, IEEE, pp. 0047, 20th IEEE VLSI Test Symposium, 2002.
 
 
BibTex
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@article{ 10.1109/VTS.2002.1011110,
author = {M. Goessel and E. Sogomonyan and A. Singh},
title = {Scan-Path with Directly Duplicated and Inverted Duplicated Registers},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2002},
isbn = {0-7695-1570-3},
pages = {0047},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011110},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Scan-Path with Directly Duplicated and Inverted Duplicated Registers
SN - 0-7695-1570-3
SP
EP
A1 - M. Goessel,
A1 - E. Sogomonyan,
A1 - A. Singh,
PY - 2002
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
M. Goessel, University of Potsdam
E. Sogomonyan, University of Potsdam
A. Singh, Auburn University
In this paper a systematic scan-path design with duplicated and inverted duplicated memory elements is proposed. Contrary to a known solution [1] no additional control lines for additional multiplexors are needed. Full controllability and observability of the proposed scan-path is demonstrated.
Citation:
M. Goessel, E. Sogomonyan, A. Singh, "Scan-Path with Directly Duplicated and Inverted Duplicated Registers," vts, pp.0047, 20th IEEE VLSI Test Symposium, 2002
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