Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture

V
VTS
2002
20th IEEE VLSI Test Symposium
Abstract - Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture

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20th IEEE VLSI Test Symposium

Monterey, California

April 28-May 02

ISBN: 0-7695-1570-3

	ASCII Text	x
	Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich, "Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture," VLSI Test Symposium, IEEE, pp. 0003, 20th IEEE VLSI Test Symposium, 2002.

	BibTex	x
	@article{ 10.1109/VTS.2002.1011103, author = {Nandu Tendolkar and Rajesh Raina and Rick Woltenberg and Xijiang Lin and Bruce Swanson and Greg Aldrich}, title = {Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2002}, isbn = {0-7695-1570-3}, pages = {0003}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011103}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture SN - 0-7695-1570-3 SP EP A1 - Nandu Tendolkar, A1 - Rajesh Raina, A1 - Rick Woltenberg, A1 - Xijiang Lin, A1 - Bruce Swanson, A1 - Greg Aldrich, PY - 2002 KW - Microprocessor KW - Delay Testing VL - 0 JA - VLSI Test Symposium, IEEE ER -

Nandu Tendolkar, Motorola, Inc.

Rajesh Raina, Motorola, Inc.

Rick Woltenberg, Motorola, Inc.

Xijiang Lin, Mentor Graphics Corporation

Bruce Swanson, Mentor Graphics Corporation

Greg Aldrich, Mentor Graphics Corporation

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011103

Scan based at-speed transition fault testing of Motorola's microprocessors based on the PowerPC(tm) instruction set architecture requires broadside transition fault test patterns that have a specific launch and capture clocking sequence. We describe the concepts we developed and incorporated in the ATPG tool to support efficient generation of such test patterns to achieve high transition fault test coverage and for analysis of undetected transition faults. Using the enhanced ATPG tool, we generated 15,000 transition fault test patterns and achieved 76% test coverage for the MPC7400 microprocessor based on the PowerPC(tm) instruction set architecture that has 10.5million transistors and runs at 540 MHz.

Index Terms:

Microprocessor, Delay Testing

Citation:

Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich, "Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture," vts, pp.0003, 20th IEEE VLSI Test Symposium, 2002

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