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19th IEEE VLSI Test Symposium
Semi-Formal Test Generation for a Block of Industrial DSP
Marina Del Rey, CA
March 29-April 03
ISBN: 0-7695-1122-8
ASCII Text
x 
 
Julia Dushina, Mike Benjamin, Daniel Geist, "Semi-Formal Test Generation for a Block of Industrial DSP," VLSI Test Symposium, IEEE, pp. 0131, 19th IEEE VLSI Test Symposium, 2001.
 
 
BibTex
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@article{ 10.1109/VTS.2001.923429,
author = {Julia Dushina and Mike Benjamin and Daniel Geist},
title = {Semi-Formal Test Generation for a Block of Industrial DSP},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2001},
isbn = {0-7695-1122-8},
pages = {0131},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2001.923429},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Semi-Formal Test Generation for a Block of Industrial DSP
SN - 0-7695-1122-8
SP
EP
A1 - Julia Dushina,
A1 - Mike Benjamin,
A1 - Daniel Geist,
PY - 2001
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Julia Dushina, STMicroelectronics
Mike Benjamin, STMicroelectronics
Daniel Geist, IBM Haifa Research Lab
This article describes an industrial application of the Genevieve test generation methodology. The Genevieve approach [1] uses formal techniques to generate test suites for specific design behaviour. The example, which is a part of the ST100 DSP, was chosen in order to highlight real life problems such as big data structures, complex control logic, and complex environments where it is difficult to determine how to drive the complete system to ensure a given behaviour in the unit under test.
Citation:
Julia Dushina, Mike Benjamin, Daniel Geist, "Semi-Formal Test Generation for a Block of Industrial DSP," vts, pp.0131, 19th IEEE VLSI Test Symposium, 2001
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