Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs

V
VTS
2001
19th IEEE VLSI Test Symposium
Abstract - Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs

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	Similar Articles Articles by Amir Attarha Articles by Mehrdad Nourani

19th IEEE VLSI Test Symposium

Marina Del Rey, CA

March 29-April 03

ISBN: 0-7695-1122-8

	ASCII Text	x
	Amir Attarha, Mehrdad Nourani, "Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs," VLSI Test Symposium, IEEE, pp. 0111, 19th IEEE VLSI Test Symposium, 2001.

	BibTex	x
	@article{ 10.1109/VTS.2001.923426, author = {Amir Attarha and Mehrdad Nourani}, title = {Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2001}, isbn = {0-7695-1122-8}, pages = {0111}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2001.923426}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs SN - 0-7695-1122-8 SP EP A1 - Amir Attarha, A1 - Mehrdad Nourani, PY - 2001 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Amir Attarha, The University of Texas at Dallas

Mehrdad Nourani, The University of Tehran

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2001.923426

We present a methodology to detect and measure the signal overshoots occurring on the interconnects of high-speed system-on-chips. Overshoots are known to inject hot-carriers into the gate oxide which cause permanent degradation of MOSFET transistors' performance over time. We propose a built-in chip mechanism to detect overshoots, collect the occurrence information and scan them out efficiently and inexpensively for built-in self-test, reliability analysis and diagnosis.

Citation:

Amir Attarha, Mehrdad Nourani, "Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs," vts, pp.0111, 19th IEEE VLSI Test Symposium, 2001

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