Planar High Performance Ring Generators

V
VTS
2004
22nd IEEE VLSI Test Symposium
Abstract - Planar High Performance Ring Generators

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22nd IEEE VLSI Test Symposium

Napa Valley, California

April 25-April 29

ISBN: 0-7695-2134-7

	ASCII Text	x
	Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, "Planar High Performance Ring Generators," VLSI Test Symposium, IEEE, pp. 193, 22nd IEEE VLSI Test Symposium, 2004.

	BibTex	x
	@article{ 10.1109/VTEST.2004.1299243, author = {Grzegorz Mrugalski and Nilanjan Mukherjee and Janusz Rajski and Jerzy Tyszer}, title = {Planar High Performance Ring Generators}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2004}, issn = {1093-0167}, pages = {193}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2004.1299243}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Planar High Performance Ring Generators SN - 1093-0167 SP EP A1 - Grzegorz Mrugalski, A1 - Nilanjan Mukherjee, A1 - Janusz Rajski, A1 - Jerzy Tyszer, PY - 2004 KW - null VL - 0 JA - VLSI Test Symposium, IEEE ER -

Grzegorz Mrugalski, Mentor Graphics Corporation, Wilsonville, OR

Nilanjan Mukherjee, Mentor Graphics Corporation, Wilsonville, OR

Janusz Rajski, Mentor Graphics Corporation, Wilsonville, OR

Jerzy Tyszer, Poznan University of Technology, Poland

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2004.1299243

The paper presents enhanced architectures of pseudo-random test pattern generators and on-chip test data decompressors based on ring generators. The new structures are aimed at improving their layout and routing properties while at the same time reducing propagation delays introduced by associated phase shifters.

Citation:

Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, "Planar High Performance Ring Generators," vts, pp.193, 22nd IEEE VLSI Test Symposium, 2004

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