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22nd IEEE VLSI Test Symposium
Detection of Temperature Sensitive Defects Using ZTC
Napa Valley, California
April 25-April 29
ISBN: 0-7695-2134-7
Ethan Long, Portland State University, Oregon
W. Robert Daasch, Portland State University, Oregon
Robert Madge, LSI Logic, Gresham
Brady Benware, LSI Logic, Fort Collins
This work attempts to improve the common understanding of multiple temperature testing by presenting previously unpublished data as well as deriving a simple model for bounding an IC's performance within the three dimensional space defined by VDD, frequency, and temperature. The model is used to design new temperature screens to improve the resolution between healthy and defective ICs. Temperature based test data is presented for Scan, LBIST, and TDF based MinVDD measurements as well as transistor characteristics needed to parameterize the model. The test vehicles used are 0.25?m and 0.18?m CMOS ASICs fabricated by LSI Logic.
Citation:
Ethan Long, W. Robert Daasch, Robert Madge, Brady Benware, "Detection of Temperature Sensitive Defects Using ZTC," vts, pp.185, 22nd IEEE VLSI Test Symposium, 2004
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