Multi-Modal Built-In Self-Test for Symmetric Microsystems

V
VTS
2004
22nd IEEE VLSI Test Symposium
Abstract - Multi-Modal Built-In Self-Test for Symmetric Microsystems

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	Similar Articles Articles by Nilmoni Deb Articles by R. D. (Shawn) Blanton

22nd IEEE VLSI Test Symposium

Napa Valley, California

April 25-April 29

ISBN: 0-7695-2134-7

	ASCII Text	x
	Nilmoni Deb, R. D. (Shawn) Blanton, "Multi-Modal Built-In Self-Test for Symmetric Microsystems," VLSI Test Symposium, IEEE, pp. 139, 22nd IEEE VLSI Test Symposium, 2004.

	BibTex	x
	@article{ 10.1109/VTEST.2004.1299237, author = {Nilmoni Deb and R. D. (Shawn) Blanton}, title = {Multi-Modal Built-In Self-Test for Symmetric Microsystems}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2004}, issn = {1093-0167}, pages = {139}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2004.1299237}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Multi-Modal Built-In Self-Test for Symmetric Microsystems SN - 1093-0167 SP EP A1 - Nilmoni Deb, A1 - R. D. (Shawn) Blanton, PY - 2004 KW - null VL - 0 JA - VLSI Test Symposium, IEEE ER -

Nilmoni Deb, Carnegie Mellon University, Pittsburgh, PA

R. D. (Shawn) Blanton, Carnegie Mellon University, Pittsburgh, PA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2004.1299237

A mathematical model analyzing the efficacy of a built-in self-test technique, applicable to any symmetrical MEMS microstructure, is developed. The model predicts that the BIST technique can also be used to characterize a wide range of local manufacturing variations affecting different regions of the device. Model predictions have been validated by simulation. Specifically, it has been shown that by using a suitable modulation scheme, sensitivity to linear etch variation along a particular direction is improved by nearly 30%.

Citation:

Nilmoni Deb, R. D. (Shawn) Blanton, "Multi-Modal Built-In Self-Test for Symmetric Microsystems," vts, pp.139, 22nd IEEE VLSI Test Symposium, 2004

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