22nd IEEE VLSI Test Symposium 3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme Napa Valley, California April 25-April 29 ISBN: 0-7695-2134-7
This paper presents a 3-stage continuous-flow linear decompression scheme for scan vectors that uses a variable number of bits to encode each vector. By using 3-stages of decompression, it can efficiently compress any test cube (i.e., deterministic test vector where the unassigned bit positions are left as don't cares) regardless of the number of specified (care) bits. As a result of this feature, there is no need for any constraints on the automatic test generation process (ATPG) process. Any ATPG can be used with any amount of static or dynamic compaction. Experimental results are shown which demonstrate that the proposed scheme achieves extremely high encoding efficiency.
Citation:
C. V. Krishna, Nur A. Touba, "3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme," vts, pp.79, 22nd IEEE VLSI Test Symposium, 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||