22nd IEEE VLSI Test Symposium Built-in Current Sensor for ∆I{DDQ} Testing of Deep Submicron Digital CMOS ICs Napa Valley, California April 25-April 29 ISBN: 0-7695-2134-7
This paper presents the implementation of a built-in current sensor that includes two recently reported new techniques for I{DDQ} testing to take into account the increased background current of defect-free circuits and its increased variance due to process variations. These techniques are the correlation between speed and I{DDQ}, and the ∆I{DDQ} testing technique. The monitor has been manufactured in a 0.18 ?m CMOS technology and it is based on the principle of disconnecting the device under test from the power supply during the testing phase. The monitor has a resolution of 1 ?A for a background current less than 100 ?A or 1% of background currents over 100 ?A to a total of 1mA full-scale. The sensor operates at a maximum clock speed of 250MHz. The monitor has been verified in a test chip consisting of one "DSP like" circuit of about 250,000 transistors. Experimental results prove the usefulness of our approach as a quick and effective means for detecting defects.
Citation:
Josep Rius V?zquez, Jos? Pineda de Gyvez, "Built-in Current Sensor for ∆I{DDQ} Testing of Deep Submicron Digital CMOS ICs," vts, pp.53, 22nd IEEE VLSI Test Symposium, 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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