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22nd IEEE VLSI Test Symposium
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
Napa Valley, California
April 25-April 29
ISBN: 0-7695-2134-7
Wangqi Qiu, Texas A&M University, College Station
Xiang Lu, Texas A&M University, College Station
Jing Wang, Texas A&M University, College Station
Zhuo Li, Texas A&M University, College Station
D. M. H. Walker, Texas A&M University, College Station
Weiping Shi, Texas A&M University, College Station
The path delay fault model is the most realistic model for delay faults. Testing all the paths in a circuit achieves 100% delay fault coverage according to traditional path delay fault coverage metrics. These metrics result in unrealistically low fault coverage if only a subset of paths is tested, and the real test quality is not reflected. For example, the traditional path delay fault coverage of any practical test for circuit c6288 is close to 0 because this circuit has an exponential number of paths. In this paper, a statistical and realistic path delay fault coverage metric is presented. Then the quality of several existing test sets (path selection methods) is evaluated in terms of local and global delay faults using this metric, in comparison with the transition fault and traditional path delay fault coverage metrics.
Citation:
Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi, "A Statistical Fault Coverage Metric for Realistic Path Delay Faults," vts, pp.37, 22nd IEEE VLSI Test Symposium, 2004
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