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22nd IEEE VLSI Test Symposium
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor
Napa Valley, California
April 25-April 29
ISBN: 0-7695-2134-7
Srikanth Venkataraman, Intel Corporation, Hillsboro, OR
Srihari Sivaraj, Intel Corporation, Hillsboro, OR
Enamul Amyeen, Intel Corporation, Hillsboro, OR
Sangbong Lee, Intel Corporation, Hillsboro, OR
Ajay Ojha, Intel Corporation, Hillsboro, OR
Ruifeng Guo, Intel Corporation, Hillsboro, OR
This paper studies the impact of N-detect scan ATPG patterns on test quality and associated test costs. An incremental method for test generation is presented. Metrics to evaluate the richness of the test set are presented. The natural N-detect profiles of regular one-detect test sets and the impact to test data volume and test time of generating additional patterns is studied. Results are presented on an Intel? Pentium? 4 processor. Simulation results from evaluating the patterns on layout extracted and random bridges are presented. Silicon data from production test shows the effectiveness of N-detect tests.
Citation:
Srikanth Venkataraman, Srihari Sivaraj, Enamul Amyeen, Sangbong Lee, Ajay Ojha, Ruifeng Guo, "An Experimental Study of N-Detect Scan ATPG Patterns on a Processor," vts, pp.23, 22nd IEEE VLSI Test Symposium, 2004
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