A Circuit Level Fault Model for Resistive Opens and Bridges

V
VTS
2003
21st IEEE VLSI Test Symposium
Abstract - A Circuit Level Fault Model for Resistive Opens and Bridges

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	Similar Articles Articles by Zhuo Li Articles by Xiang Lu Articles by Wangqi Qiu Articles by Weiping Shi Articles by D. M. H. Walker

21st IEEE VLSI Test Symposium

Napa Valley, California

April 27-May 01

ISBN: 0-7695-1924-5

	ASCII Text	x
	Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker, "A Circuit Level Fault Model for Resistive Opens and Bridges," VLSI Test Symposium, IEEE, pp. 379, 21st IEEE VLSI Test Symposium, 2003.

	BibTex	x
	@article{ 10.1109/VTEST.2003.1197678, author = {Zhuo Li and Xiang Lu and Wangqi Qiu and Weiping Shi and D. M. H. Walker}, title = {A Circuit Level Fault Model for Resistive Opens and Bridges}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2003}, issn = {1093-0167}, pages = {379}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197678}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - A Circuit Level Fault Model for Resistive Opens and Bridges SN - 1093-0167 SP EP A1 - Zhuo Li, A1 - Xiang Lu, A1 - Wangqi Qiu, A1 - Weiping Shi, A1 - D. M. H. Walker, PY - 2003 KW - null VL - 0 JA - VLSI Test Symposium, IEEE ER -

Zhuo Li, Texas A&M University

Xiang Lu, Texas A&M University

Wangqi Qiu, Texas A&M University

Weiping Shi, Texas A&M University

D. M. H. Walker, Texas A&M University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197678

Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are modeled. In this paper, we propose a circuit level model for resistive open and bridge faults. All possible fault behaviors are illustrated and a general resistive bridge delay calculation method is proposed. The new models are practical and easy to use. Fault simulation results show that the new models help the delay test to catch more bridge faults.

Citation:

Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker, "A Circuit Level Fault Model for Resistive Opens and Bridges," vts, pp.379, 21st IEEE VLSI Test Symposium, 2003

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