21st IEEE VLSI Test Symposium SOC Test Scheduling Using Simulated Annealing Napa Valley, California April 27-May 01 ISBN: 0-7695-1924-5
We propose an SOC test scheduling method based on simulated annealing. In our method, the test scheduling is formulated as a two-dimensional bin packing problem (rectangle packing) and a data structure called a sequence pair is used to represent the placement of the rectangles. Simulated annealing is used to find the optimal test schedule by altering an initial sequence pair and changing the width of the core wrapper. We also propose a method of wrapper design for cores without internal scan chains. Experiments are conducted on ITC?02 benchmarks, showing that overall the proposed method provides better solutions compared to earlier methods.
Citation:
Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang, "SOC Test Scheduling Using Simulated Annealing," vts, pp.325, 21st IEEE VLSI Test Symposium, 2003 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||