The ITRS (International Technology Roadmap for Semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing demands for performance. Such scaling will result in an exponential increase in leakage current and large variability in threshold voltage both within and across dies. Device counts will increase from about 0.2B/chip today to approximately 10B/chip in a decade. This 50X increase in device count will increase not only the active power dissipation, but also the standby or the quiescent power. Hence, designers are required to use innovative aggressive power management strategies to meet the power constraints. The exponential increase in leakage, the device parameter variations, and aggressive power management techniques are expected to severely impact the way integrated circuits are tested today. This paper explores test considerations for the scaled CMOS circuits in the nanometer regime.