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21st IEEE VLSI Test Symposium
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit
Napa Valley, California
April 27-May 01
ISBN: 0-7695-1924-5
ASCII Text
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Irith Pomeranz, Sudhakar M. Reddy, "On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit," VLSI Test Symposium, IEEE, pp. 173, 21st IEEE VLSI Test Symposium, 2003.
 
 
BibTex
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@article{ 10.1109/VTEST.2003.1197648,
author = {Irith Pomeranz and Sudhakar M. Reddy},
title = {On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2003},
issn = {1093-0167},
pages = {173},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197648},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit
SN - 1093-0167
SP
EP
A1 - Irith Pomeranz,
A1 - Sudhakar M. Reddy,
PY - 2003
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Irith Pomeranz, Purdue University
Sudhakar M. Reddy, University of Iowa
When storage requirements or limits on test application time do not allow a complete (compact) test set to be used for a circuit, a partial test set that detects as many faults as possible is required. Motivated by this application, we address the following problem. Given a test sequence T of length L for a synchronous sequential circuit and a length M S of length at most M such that the fault coverage of TS is maximal. A similar problem was considered before for combinational and scan circuits, and solved by test ordering. Test ordering is not possible with the single test sequence considered here. We solve this problem by using a vector omission process that allows the length of the sequence T to be reduced while allowing controlled reductions in the number of detected faults. In this way, it is possible to obtain a sequence TS that has the desired length and a maximal fault coverage.
Citation:
Irith Pomeranz, Sudhakar M. Reddy, "On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit," vts, pp.173, 21st IEEE VLSI Test Symposium, 2003
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