21st IEEE VLSI Test Symposium Automatic Configuration Generation for FPGA Interconnect Testing Napa Valley, California April 27-May 01 ISBN: 0-7695-1924-5
We present a new automatic test configuration generation technique for manufacturing testing of interconnect network of SRAM-based FPGA architectures. The technique guarantees detection of open and bridging faults in all wiring channels and programmable switches in the interconnects. Only 8 test configurations are required to achieve 100% coverage of stuck-open, stuck-closed, open and bridging faults in the interconnects of Xilinx Virtex FPGAs.
Citation:
Mehdi Baradaran Tahoori, Subhasish Mitra, "Automatic Configuration Generation for FPGA Interconnect Testing," vts, pp.134, 21st IEEE VLSI Test Symposium, 2003 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||