In sub-micron processes, resistive path defects are increasingly contributing to the yield loss and the customer fail pareto. Data has been collected on a series of ASIC products and compares the effectiveness of full vector set transition delay fault tests with reduced vector sets, minVDD, customer functional tests and customers system fails. Results show that fault models do not predict the defect coverage well and cost effective screening of frequency outliers and minVDD outliers is possible and is critical in improving customer quality.