Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs

V
VTS
2003
21st IEEE VLSI Test Symposium
Abstract - Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs

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	Similar Articles Articles by Magdy Abadir Articles by Juhong Zhu

21st IEEE VLSI Test Symposium

Napa Valley, California

April 27-May 01

ISBN: 0-7695-1924-5

	ASCII Text	x
	Magdy Abadir, Juhong Zhu, "Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs," VLSI Test Symposium, IEEE, pp. 22, 21st IEEE VLSI Test Symposium, 2003.

	BibTex	x
	@article{ 10.1109/VTEST.2003.1197629, author = {Magdy Abadir and Juhong Zhu}, title = {Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2003}, issn = {1093-0167}, pages = {22}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197629}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs SN - 1093-0167 SP EP A1 - Magdy Abadir, A1 - Juhong Zhu, PY - 2003 KW - null VL - 0 JA - VLSI Test Symposium, IEEE ER -

Magdy Abadir, Motorola

Juhong Zhu, Motorola

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197629

In this paper, we presente a new transition ATPG methodology flow for scan-base design using broad-side test format. A Replicate and Reduce (RR) circuit transform is introduced, which maps the two time frame processing of transition fault ATPG to a single time frame processing on duplicate iterative blocks with reduced connection. A complete ATPG methodology flow is proposed to generate high coverage transition test patterns both fast and efficiently. Experimentation results on several circuits from next generation Motorola microprocessor design are presented to show the effectiveness of our approach.

Citation:

Magdy Abadir, Juhong Zhu, "Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs," vts, pp.22, 21st IEEE VLSI Test Symposium, 2003

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