Thermal Testing: Fault Location Strategies

V
VTS
2000
18th IEEE VLSI Test Symposium (VTS'00)
Abstract - Thermal Testing: Fault Location Strategies

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18th IEEE VLSI Test Symposium (VTS'00)

Montreal, Canada

April 30-May 04

ISBN: 0-7695-0613-5

	ASCII Text	x
	J. Altet, A. Rubio, E. Schaub, S. Dialhaire, W. Claeys, "Thermal Testing: Fault Location Strategies," VLSI Test Symposium, IEEE, pp. 189, 18th IEEE VLSI Test Symposium (VTS'00), 2000.

	BibTex	x
	@article{ 10.1109/VTEST.2000.843844, author = {J. Altet and A. Rubio and E. Schaub and S. Dialhaire and W. Claeys}, title = {Thermal Testing: Fault Location Strategies}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2000}, issn = {1093-0167}, pages = {189}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843844}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Thermal Testing: Fault Location Strategies SN - 1093-0167 SP EP A1 - J. Altet, A1 - A. Rubio, A1 - E. Schaub, A1 - S. Dialhaire, A1 - W. Claeys, PY - 2000 KW - Thermal Testing KW - Temperature Measurements KW - Built-In Differential Temperature Sensors KW - Fault Location KW - Mixed-Signal Circuits VL - 0 JA - VLSI Test Symposium, IEEE ER -

J. Altet, Polytechnical University of Catalonia (UPC)

A. Rubio, Polytechnical University of Catalonia (UPC)

E. Schaub, Universite Bordeaux 1

S. Dialhaire, Universite Bordeaux 1

W. Claeys, Universite Bordeaux 1

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843844

By measuring the temperature at some points of an IC during a test procedure, defects can be detected (fault testing). With a simple processing of the measured temperature waveform, the distance between the temperature monitoring point and the activated defect can be derived. This paper presents four temperature-measuring strategies to determine this distance for diagnosis purposes.

Index Terms:

Thermal Testing, Temperature Measurements, Built-In Differential Temperature Sensors, Fault Location, Mixed-Signal Circuits

Citation:

J. Altet, A. Rubio, E. Schaub, S. Dialhaire, W. Claeys, "Thermal Testing: Fault Location Strategies," vts, pp.189, 18th IEEE VLSI Test Symposium (VTS'00), 2000

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