Self-Checking Circuits versus Realistic Faults in Very Deep Submicron

V
VTS
2000
18th IEEE VLSI Test Symposium (VTS'00)
Abstract - Self-Checking Circuits versus Realistic Faults in Very Deep Submicron

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Lorena Anghel Articles by Michael Nicolaidis Articles by Issam Alzaher-Noufal

18th IEEE VLSI Test Symposium (VTS'00)

Montreal, Canada

April 30-May 04

ISBN: 0-7695-0613-5

	ASCII Text	x
	Lorena Anghel, Michael Nicolaidis, Issam Alzaher-Noufal, "Self-Checking Circuits versus Realistic Faults in Very Deep Submicron," VLSI Test Symposium, IEEE, pp. 55, 18th IEEE VLSI Test Symposium (VTS'00), 2000.

	BibTex	x
	@article{ 10.1109/VTEST.2000.843827, author = {Lorena Anghel and Michael Nicolaidis and Issam Alzaher-Noufal}, title = {Self-Checking Circuits versus Realistic Faults in Very Deep Submicron}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2000}, issn = {1093-0167}, pages = {55}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843827}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Self-Checking Circuits versus Realistic Faults in Very Deep Submicron SN - 1093-0167 SP EP A1 - Lorena Anghel, A1 - Michael Nicolaidis, A1 - Issam Alzaher-Noufal, PY - 2000 KW - Concurrent checking KW - self–checking circuits KW - defects KW - soft errors KW - timing faults KW - very deep submicron KW - nanometer technologies KW - hardware fault tolerance VL - 0 JA - VLSI Test Symposium, IEEE ER -

Lorena Anghel, TIMA

Michael Nicolaidis, TIMA

Issam Alzaher-Noufal, TIMA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843827

IC technologies are approaching the ultimate limits of silicon in terms of device size, power supply levels and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise as well as to small manufacturing defects that may result on spurious faults. Such faults are difficult to (or can not) be detected by manufacturing testing and will result on unacceptable rates of errors in the field. Self-checking design can be used to cope with this problem, but usually it addresses logic faults. This paper analyzes the behavior of self-checking circuits under various spurious faults likely to occur in very deep submicron technologies.

Index Terms:

Concurrent checking, self–checking circuits, defects, soft errors, timing faults, very deep submicron, nanometer technologies, hardware fault tolerance

Citation:

Lorena Anghel, Michael Nicolaidis, Issam Alzaher-Noufal, "Self-Checking Circuits versus Realistic Faults in Very Deep Submicron," vts, pp.55, 18th IEEE VLSI Test Symposium (VTS'00), 2000

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.